MAIN BASED UNIT SPECIFICATION
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System incorporated advanced ASIC design technology with built-in digital logic libraries
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Solderless Breadboard - Interconnected nickel-plated contact with 1680
ti
e-points
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DC Power Supply:
o
Variable 0 ~ ± 20 VDC / 500mA
o
Fixed +3.3 VDC / 800mA
o
Fixed +5 VDC / 1A
o
Fixed +12 VDC / 500mA
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16-Bit Output LEDs
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16-Bit Data Input Switches (3.3 VDC)
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Two (2) Pulse Switches (3.3 VDC)
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Built-in Buzzer x1
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Programming state indicators
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GPIO pins on board (24 inputs and 44 Outputs) via standard DIL pin headers
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Intelligent Logic Probe with 7-Segment LED indicator
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USB Port type B x1
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Two (2) 7-Segment LED Displays with BCD decoder and HEX decoder drivers (selectable)
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Pulse Signal Clock Generator (Variable): -
o
Frequency Ranges:
▪
1Hz ~ 10Hz
▪
10Hz ~ 100Hz
▪
100Hz ~ 1kHz
▪
1KHz ~ 10kHz
▪
10kHz ~ 100kHz
▪
100kHz ~ 1MHz
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Output: TTL and variable amplitude output
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Fixed clock outputs: - 1 Hz, 10 Hz, 100Hz, 1kHz, 10kHz, 100kHz, 1 MHz, 10 MHz
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Input supply: 240VAC/50Hz
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Mains On/Off switch with indicator and overload protec
ti
on with fuse
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Dimensions: 375mm x 220mm x 110mm (WxDxH) approx.
EXPERIMENT SPECIFICATION (INTERGRATED LOGIC LIBRARIES)
1
.
Basic Logic Gate
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AND gate: 2 inputs, 3 inputs, 4 inputs
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OR gate: 2 inputs, 3 inputs, 4 inputs
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NAND gate: 2 inputs, 3 inputs, 4 inputs,
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NOR gate: 2 inputs, 3 inputs, 4 inputs
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NOT gate
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XOR gate
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XNOR gate
2. Basic Combina
ti
on Gate
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AND-OR conversion
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OR-AND conversion
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NOR-NAND conversion
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NAND-NOR conversion
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NAND as inverter
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NAND as AND
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NAND as OR
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NAND as NOR
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NOR as inverter
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NOR as OR
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NOR as AND
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NOR as NAND
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AND + NOT
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NOT + AND
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NOT + AND + NOT
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NAND + NOT
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NOT + NAND
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NOT + NAND + NOT
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OR + NOT
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NOT + OR
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NOT + OR + NOT
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NOR + NOT
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NOT + NOR
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NOT + NOR + NOT
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NOT + NOT
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NOT + NOT + NOT
3. Combina
ti
on Logic 1
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Binary half adder
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Binary full adder
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Binary half subtractor
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Binary full subtractor
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Parallel adders
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Comparators
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Binary to fray code conversion
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Gray code to binary conversion
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Parity checker
4. Combina
ti
on Logic 2
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4-bit binary decoder
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BCD-DEC decoder
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4-to-16-line decoder
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DEC-BCD encoder
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DEC-BCD priority encoder
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8-to-3 priority line encoder
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Mul
ti
plexer
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De-mul
ti
plexer
5. Sequential Logic
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D flip-flop
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SR flip-flop
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JK flip-flop
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T flip-flop
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Synchronous binary counters
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Synchronous up/down counters
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Synchronous BCD decade counters
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Asynchronous binary counters
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Asynchronous mode-N counters
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Data storage registers
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Parallel in parallel out shi
ft
registers
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Serial in serial out shift registers
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Serial in parallel out shft registers
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Parallel in serial out shft registers
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Binary ring counter
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Johnson counter
6. Tri-state
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Tri-state inverter
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Tri-state buffer
COMPUTER SYSTEM REQUIREMENT (Min)
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CPU Intel i5
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Memory: 8GB RAM
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Storage: 500MB
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USB Ports x4
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Opera
ti
ng system: Windows 10/11 (64-bit)
MANUAL & ACCESSORIES
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Opera
ti
on / User Manual x 1
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Lab Experiment Workbook x 1
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ABLELOGIC™ (GUI) Ver 1.0 system so
ft
ware installer x1
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USB Cable x1
•
Power Cord x 1
•
Connec
ti
ng Jumper Cables x 1 set
•
Spare Fuse x 2
